A–14 Alpha Instruction Set
Alpha 21264/EV67 Hardware Reference Manual
IEEE Floating-Point Conformance
A.8 IEEE Floating-Point Conformance
The 21264/EV67 supports the IEEE floating-point operations defined in the Alpha Sys-
tem Reference Manual, Revision 7 and therefore also from the Alpha Architecture
Handbook, Version 4. Support for a complete implementation of the IEEE Standard for
Binary Floating-Point Arithmetic (ANSI/IEEE Standard 754 1985) is provided by a
combination of hardware and software. The 21264/EV67 provides several hardware
features to facilitate complete support of the IEEE standard.
The 21264/EV67 provides the following hardware features to facilitate complete sup-
port of the IEEE standard:
• The 21264/EV67 implements precise exception handling in hardware, as denoted
by the AMASK instruction returning bit 9 set. TRAPB instructions are treated as
NOPs and are not issued.
• The 21264/EV67 accepts both Signaling and Quiet NaNs as input operands and
propagates them as specified by the Alpha architecture. In addition, the 21264/
EV67 delivers a canonical Quiet NaN when an operation is required to produce a
NaN value and none of its inputs are NaNs. Encodings for Signaling NaN and
Quiet NaN are defined by the Alpha Architecture Handbook, Version 4.
• The 21264/EV67 accepts infinity operands and implements infinity arithmetic as
defined by the IEEE standard and the Alpha Architecture Handbook, Version 4.
• The 21264/EV67 implements SQRT for single (SQRTS) and double (SQRTT) pre-
cision in hardware.
Note: In addition, the 21264/EV67 also implements the VAX SQRTF and
SQRTG instructions.
• The 21264/EV67 implements the FPCR[DNZ] bit. When FPCR[DNZ] is set,
denormal input operand traps can be avoided for arithmetic operations that include
the /S qualifier. When FPCR[DNZ] is clear, denormal input operands for arithmetic
operations produce an unmaskable denormal trap. CPYSE/CPYSN, FCMOVxx,
and MF_FPCR/MT_FPCR are not arithmetic operations, and pass denormal values
without initiating arithmetic traps.
• The 21264/EV67 implements the following disable bits in the floating-point control
register (FPCR):
– Underflow disable (UNFD)
– Overflow disable (OVFD)
– Inexact result disable (INED)
– Division by zero disable (DZED)
– Invalid operation disable (INVD)
If one of these bits is set, and an instruction with the /S qualifier set generates the
associated exception, the 21264/EV67 produces the IEEE nontrapping result and
suppresses the trap. These nontrapping responses include correctly signed
infinity, largest finite number, and Quiet NaNs as specified by the IEEE
standard.
