Performance Tuning
Guidelines
A cell should be configured with a multiple of 8 DIMMs. It takes 8 DIMMs to populate both
buses. Populating only one of the two memory buses on a cell board will deliver only half the
peak memory bandwidth.
Load memory equally across the available cell boards.
If growth is planned for the system, then plan on configuring high density 4GB, 8-GB, or 16-
GB modules to minimize future memory slot constraints.
Memory Latencies
There are two types of memory latencies within the HP 9000 rp7420 Server:
1. Memory latency
within
the cell refers to the case where an application either runs on a partition
that consists of a single cell or uses cell local memory.
2. Memory latency
between
cells refers to the case where the partition consists of two cells and
cell interleaved memory is used. In this case 50% of the addresses are to memory on the same
cell as the requesting processor, and the other 50% of the addresses are to memory of the other
cell.
The HP 9000 rp7420 Server average memory latency depends on the number of processors in
the partition. Assuming that memory accesses are equally distributed across all cell boards and
memory controllers within the partition, the average idle memory latency (load-to-use) is as show
below:
Number of processor modules
Average Memory Latency
4-dual core processor modules (single cell)
~241 ns
8-dual core processor modules (two cell)
~292 ns
I/O Architecture
Components within the I/O subsystem are the I/O controllers, internal peripheral bay, and
multifunction Core I/O. The figure below shows the basic block diagram of the I/O subsystem. The
HP 9000 rp7420 Server I/O architecture utilizes industry standard PCI buses in a unique design
for maximum performance, scalability and reliability.
The HP Integrity rp7420 Server contains two master I/O controller chips located on the PCI-X
backplane. Each I/O controller contains 16 high-performance, 12-bit-wide links; these links
connect to 18 slave I/O controller chips supporting the PCI card slots and core I/O. In the HP 9000
rp7420 Server, two links, one from each master controller, are routed through the system
backplane and are dedicated to core I/O. The remaining thirty links are divided among the sixteen
I/O card slots. This one card per link architecture leads to greater I/O performance and higher
availability. Each controller chip is also directly linked to a host cell board. This means that both
cell boards must be purchased in order to access all 15 available I/O card slots. (With only one
cell board, access to seven expansion slots is enabled.)
The HP 9000 rp7420 Server can be purchased with either one or two core I/O board sets. Each
Core I/O product contains two boards, a MP/SCSI and a LAN/SCSI card. The core I/O boards
provide console, Ultra160 SCSI, Gigabit LAN, serial, and management processor functionality. If
you opt for the second core I/O board set, it can be used to enable dual hard partitioning (nPars)
in the HP 9000 rp7420 Server and to provide access to a second set of disk drives.
The LAN/SCSI card provided with each Core I/O product occupies one of the sixteen PCI slots.
Since there must always be at least one Core I/O board set, the HP 9000 rp7420 Server has
fifteen available PCI slots for expansion cards. If the second Core I/O product (board set) is
purchased, there are fourteen remaining slots available for expansion cards.
The internal peripheral bay supports up to four low-profile disks and one removable-media device.
The internal disks are electrically divided into two pairs. SCSI controller chips located on each
QuickSpecs
HP 9000 rp7420 Server
Configuration
DA - 11895 U.S. QuickSpecs — Version 24 — 10/1/2006
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