Intel GD82559ER Manual

A SERVICE OF

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GD82559ER — Networkin

g

Silicon

8

Datasheet

3.2.2 Interface Control Si

g

nals

Symbol Type Name and Function

FRAME# S/T/S

Cycle Frame.

The c

y

cle frame si

g

nal is driven b

y

the current master

to indicate the be

g

innin

g

and duration of a transaction. FRAME# is

asserted to indicate the start of a transaction and de-asserted durin

g

the final data phase.

IRDY# S/T/S

Initiator Ready.

The initiator read

y

si

g

nal indicates the bus master’s

abilit

y

to complete the current data phase and is used in con

j

unction

with the tar

g

et read

y

(

TRDY#

)

si

g

nal. A data phase is completed on

an

y

clock c

y

cle where both IRDY# and TRDY# are sampled asserted

(

low

)

simultaneousl

y

.

TRDY# S/T/S

Target Ready.

The tar

g

et read

y

si

g

nal indicates the selected device’s

abilit

y

to complete the current data phase and is used in con

j

unction

with the initiator read

y

(

IRDY#

)

si

g

nal. A data phase is completed on

an

y

clock c

y

cle where both IRDY# and TRDY# are sampled asserted

(

low

)

simultaneousl

y

.

STOP# S/T/S

Stop.

The stop si

g

nal is driven b

y

the tar

g

et to indicate to the initiator

that it wishes to stop the current transaction. As a bus slave, STOP# is

driven b

y

the 82559ER to inform the bus master to stop the current

transaction. As a bus master, STOP# is received b

y

the 82559ER to

stop the current transaction.

IDSEL IN

Initialization Device Select.

The initialization device select si

g

nal is

used b

y

the 82559ER as a chip select durin

g

PCI confi

g

uration read

and write transactions. This si

g

nal is provided b

y

the host in PCI

s

y

stems.

DEVSEL# S/T/S

Device Select.

The device select si

g

nal is asserted b

y

the tar

g

et once

it has detected its address. As a bus master, the DEVSEL# is an input

si

g

nal to the 82559ER indicatin

g

whether an

y

device on the bus has

been selected. As a bus slave, the 82559ER asserts DEVSEL# to

indicate that it has decoded its address as the tar

g

et of the current

transaction.

REQ# T/S

Request.

The re

q

uest si

g

nal indicates to the bus arbiter that the

82559ER desires use of the bus. This is a point-to-point si

g

nal and

ever

y

bus master has its own REQ#.

GNT# IN

Grant.

The

g

rant si

g

nal is asserted b

y

the bus arbiter and indicates to

the 82559ER that access to the bus has been

g

ranted. This is a point-

to-point si

g

nal and ever

y

master has its own GNT#.

INTA# O/D

Interrupt A.

The interrupt A si

g

nal is used to re

q

uest an interrupt b

y

the 82559ER. This is an active low, level tri

gg

ered interrupt si

g

nal.

SERR# O/D

System Error.

The s

y

stem error si

g

nal is used to report address

parit

y

errors. When an error is detected, SERR# is driven low for a

sin

g

le PCI clock.

PERR# S/T/S

Parity Error.

The parit

y

error si

g

nal is used to report data parit

y

errors

durin

g

all PCI transactions except a Special C

y

cle. The parit

y

error pin

is asserted two clock c

y

cles after the error was detected b

y

the device

receivin

g

data. The minimum duration of PERR# is one clock for each

data phase where an error is detected. A device cannot report a parit

y

error until it has claimed the access b

y

assertin

g

DEVSEL# and

completed a data phase.