A SERVICE OF

logo

INTER0
INTER1
INTER3
INTER2
Base 0
Base 2
Base 4
Base 6
INTER2
INTER3
INTER1
INTER0
EDMA3
63 0
INTER3
INTER2
INTER1
INTER0
Kernel
63 0
TCP
Memory
Endian_Intr=1
Endianness
manager
7.1.3.2ENDIAN_INTR=0
INTER1
INTER0
INTER2
INTER3
Base 0
Base 2
Base 4
Base 6
INTER3
INTER2
INTER0
INTER1
EDMA3
63 0
INTER3
INTER2
INTER1
INTER0
Kernel
63 0
TCP
Memory
Endian_Intr=0
Endianness
manager
Endianness
www.ti.com
Figure83.InterleaverIndexesinDSPMemory(ENDIAN_INTR=1)
TheyhavetobeswappedasdescribedinFigure84andFigure85.
Figure84.DataSource-EDMA3(ENDIAN_INTR=1)
634847323116151
INTER0INTER1INTER2INTER3
Figure85.DataDestination-Kernel(ENDIAN_INTR=1)
634847323116151
INTER3INTER2INTER1INTER0
IfENDIAN_INTR=0,dataaresavedinwordpackedformat(32bits)intheDSP(seeTable36).
Table36.InterleaverIndexesinDSPMemory
(ENDIAN_INTR=0)
Address(hexbytes)Data
BaseINTER1
Base+2INTER0
Base+4INTER3
Base+6INTER2
Figure86.InterleaverIndexesinDSPMemory(ENDIAN_INTR=0)
TheyhavetobeswappedasdescribedinFigure87andFigure88.
56TMS320C6457Turbo-DecoderCoprocessor2SPRUGK1March2009
SubmitDocumentationFeedback