Dell T610 Manual

A SERVICE OF

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Dell™ PowerEdge™ T610 Technical Guidebook

28

Advanced ECC mode and the SDDC code. Correction of a x4 device failure is possible through Memory

Optimized mode.

 •

If DIMMs of dierent speeds are mixed, all channels will operate at the fastest common frequency.

 •RDIMMsandUDIMMscannotbemixed.

 •Ifmemorymirroringisenabled,identicalDIMMsmustbeinstalledinthesameslotsacrossboth

channels. The third channel of each processor is unavailable for memory mirroring.

 •

The ﬁrst DIMM slot in each channel is color‑coded with white ejection tabs for ease of installation

.

 •TheDIMMsocketsareplaced450mils(11.43mm)apart,center-to-centerinordertoprovide

enough space for sucient airﬂow to cool stacked DIMMs.

 •

The PowerEdge T610 supports up to 12 DIMMs. DIMMs must be installed in each channel starting

with the DIMM slot farthest from the processor. Population order is identiﬁed by the silkscreen

designator and the System Information Label (SIL) label located on the cooling shroud.

  •Independent:{1,2,3},{4,5,6}

  •LocksteporMirrored:{2,3},{5,6}

  •QuadRankorUDIMM:{1,2,3},{4,5,6}

C. Speed

The memory frequency is determined by a variety of inputs:

 •SpeedoftheDIMMs

 •SpeedsupportedbytheCPU

 •CongurationoftheDIMMs

NOTE: For Quad Rank DIMMs mixed with Single‑ or Dual‑Rank DIMMs, the QR DIMM needs to be in the

slot with the white ejection tabs (the ﬁrst DIMM slot in each channel). There is no requirement for the

order of SR and DR DIMMs