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Pin No. Terminal In/Out Function
1 ~ 8 CD0 ~ CD7 In/Out Data bus
9, 10 CE1, TRSB — Not used
11 GND7 In Ground (0 V) source
12 CK16 Out Terminal for 24.576 MHz clock check point
13 VCC6 In +5 V source
14 CK0 In Clock input. Connected to terminal CK16.
15 TCKB — Not used
16 VCC1 In +5 V source
17 GND1 In Ground (0 V) source
18, 19 XT0, XT1 In/Out 24.576 MHz clock input/output
20 SGL In System control terminal. Single chip system: Open
21 CCSB In Chip select signal input
22 ~ 25 CA0 ~ CA3 In Address bus
26 CE0 In Not used. Connected to ground.
27 CWRB In Write enable signal
28 CRDB In Read enable signal
29 ~ 32 — — Not used
33 RESB In Reset signal input
34 TESB In Not used. Connected to +5 V.
35 ~ 39 — — Not used
40 ~ 49
52 ~ 57
50 VCC2 In +5 V source
51 GND2 In Ground (0 V) source
58 RA23 Out Not used
59 RA22 Out Chip select signal for the sound source ROM
60 RA21 Out Not used
61 ~ 73
75 ~ 82
74 GND5 In Ground (0 V) source
83 WOK2 Out Not used
84 VCC3 In +5 V source
85 GND3 In Ground (0 V) source
86 WOK1 Out Word clock for the DAC
87 SOLM Out Not used
88 SOLP Out Serial sound data output
89 BOK Out Bit clock output
90 ~ 92 — — Not used
93 VCC5 In +5 V source
94, 95
97 ~ 105
107, 109
110, 112
96 EWEB Out Write enable signal for the effect RAM
RD0 ~ RD15 Data bus for the sound source ROMIn
RA0 ~ RA20 Address bus for the sound source ROMOut
EA0 ~ EA14 Address bus for the effect RAMOut