1-4 Vol. 3
ABOUT THIS MANUAL
Chapter 6 — Interrupt and Exception Handling. Describes the basic interrupt
mechanisms defined in the Intel 64 and IA-32 architectures, shows how interrupts
and exceptions relate to protection, and describes how the architecture handles each
exception type. Reference information for each exception is given at the end of this
chapter.
Chapter 7 — Task Management. Describes mechanisms the Intel 64 and IA-32
architectures provide to support multitasking and inter-task protection.
Chapter 8 — Multiple-Processor Management. Describes the instructions and
flags that support multiple processors with shared memory, memory ordering, and
Intel
®
Hyper-Threading Technology.
Chapter 9 — Processor Management and Initialization. Defines the state of an
Intel 64 or IA-32 processor after reset initialization. This chapter also explains how to
set up an Intel 64 or IA-32 processor for real-address mode operation and protected-
mode operation, and how to switch between modes.
Chapter 10 — Advanced Programmable Interrupt Controller (APIC).
Describes the programming interface to the local APIC and gives an overview of the
interface between the local APIC and the I/O APIC.
Chapter 11 — Memory Cache Control. Describes the general concept of caching
and the caching mechanisms supported by the Intel 64 or IA-32 architectures. This
chapter also describes the memory type range registers (MTRRs) and how they can
be used to map memory types of physical memory. Information on using the new
cache control and memory streaming instructions introduced with the Pentium III,
Pentium 4, and Intel Xeon processors is also given.
Chapter 12 — Intel
®
MMX™ Technology System Programming. Describes
those aspects of the Intel
®
MMX™ technology that must be handled and considered
at the system programming level, including: task switching, exception handling, and
compatibility with existing system environments.
Chapter 13 — System Programming For Instruction Set Extensions And
Processor Extended States. Describes the operating system requirements to
support SSE/SSE2/SSE3/SSSE3/SSE4 extensions, including task switching, excep
-
tion handling, and compatibility with existing system environments. The latter part of
this chapter describes the extensible framework of operating system requirements to
support processor extended states. Processor extended state may be required by
instruction set extensions beyond those of SSE/SSE2/SSE3/SSSE3/SSE4 extensions.
Chapter 14 — Power and Thermal Management. Describes facilities of Intel 64
and IA-32 architecture used for power management and thermal monitoring.
Chapter 15 — Machine-Check Architecture. Describes the machine-check
architecture and machine-check exception mechanism found in the Pentium
4, Intel Xeon, and P6 family processors
. Additionally, a signaling mechanism
for software to respond to hardware corrected machine check error is
covered.
