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MB15F74UL
9
(2) Data setting
•
Binary 14-bit Programmable Reference Counter Data Setting
Note : Divide ratio less than 3 is prohibited.
•
Binary 11-bit Programmable Counter Data Setting
Note : Divide ratio less than 3 is prohibited
•
Binary 7-bit Swallow Counter Data Setting
Divide ratio R14R13R12R11R10R9R8R7R6R5R4R3R2R1
3 00000000000011
4
•
•
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16383
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
1
•
•
•
1
0
•
•
•
1
0
•
•
•
1
Divide ratioN11N10N9N8N7N6N5N4N3N2N1
3 00000000011
4
•
•
•
2047
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
1
•
•
•
1
0
•
•
•
1
0
•
•
•
1
Divide ratioA7A6A5A4A3A2A1
0 0000000
1
•
•
•
127
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
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•
•
1
0
•
•
•
1
0
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•
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1
1
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•
•
1
• Programmable Counter
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047)
LDS : LD/fout signal select bit
SW
IF/RF : Divide ratio setting bit for the prescaler (IF : SWIF, RF : SWRF)
FCIF/RF : Phase control bit for the phase detector (IF : FCIF, RF : FCRF)
CN1, 2 : Control bit
Note : Data input with MSB first.
1 2 3 4 5 6 7 8 9 101112131415161718192021 22 23
CN1 CN2 LDS
SW
IF/
RF
FCIF/
RF
A1 A2 A3 A4 A5 A6 A7
N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
(LSB)
(MSB)
Data Flow