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©2000 Crown International, Inc.
IQ-USM 810 Service Manual
3-4 Circuit Theory
130447-1 Rev. A
Each DAC takes a 2 channel I
2
S 32-bit time-division
multiplexed data audio stream from the SHARC PWA
and converts it at a 24-bit, 48-kHz rate (Figure 3.4). Like
the A/D converter, the audio output of the DAC is bi-
ased positive by 2.2V and a full signal is 2.82Vp-p.
3.4.3 Output Analog Processing
All ten analog output channels are identical (Figure 3.6).
The balanced output of the DAC drives a unity gain
amplifier that also filters the audio signal. The single-
ended output is fed to U101A which provides gain of
either 1.2 (+10 dbu) or 3.9 (+20 dbu). Z100 is normally
open, which provides a +20 dbu output for a full scale
signal from the DAC. U101C provides a gain reduction
of 2, then U101D inverts the signal and provides the
other balanced output. An output impedance of 50 ohms
is provided by the series resistors while the output fer-
rite bead provides RF filtering to ensure isolation. Op-
tional isolation transformers are available on the Main
outputs by removing the series resistors and placing
the transformers.
Figure 3.5 Output PWA Block Diagram
used. This data is routed to the SHARC PWA for pro-
cessing (ADC1-4). Figure 3.4 shows the audio data and
its relationship to the clock signals.
3.3.4 DC Voltages
The Input PWA receives +/–15V and +5V from the Sys-
tem Controller. +15V from P900 is filtered and then regu-
lated by a low dropout regulator, U900. R900 & R901
set the output voltage of the regulator at +14.5V. The
–15V is processed similarly by U901. The +5V is filtered
separately for the digital portion of the PWA than the
analog side.
The phantom power voltage is generated by U902. +15V
from P900 drives L904 while Q900 acts as a switch to
charge L904. R905 acts as a current sense and limits
the output current of the phantom power by reducing
the voltage at currents over 50 mA. R904 & R908 set
the output voltage at about +26V. U902 is driven from a
96-kHz clock provided by U10. This ensures that the
switching supply is synced to the sampling frequency
of the converters (2Fs). During reset, U902 will run at a
slightly lower frequency due to the lack of an input clock.
3.4 Output
The Output PWA sits on top of the Input
PWA and provides 10 audio outputs; Main
A/B and AUX 1-8. The Output PWA re-
ceives all of its signals from the Input PWA
via a 26-pin ribbon cable. Functionality
can be divided into Clock Buffers, DAC
Conversion, and Output Analog Process-
ing. A block diagram of the Output PWA
is shown in Figure 3.5.
3.4.1 Clock Buffers
Three clock buffers, U1-3, accept the Mas-
ter (12.288 MHz), Serial (3.032 MHz), and
Frame (48 kHz) clocks from the Input PWA
and provide separate outputs to each of
the five DAC's.
3.4.2 DAC Conversion
Figure 3.4 Audio Data and Clock Signals