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[Regarding the clock source
of
this unit]
SECTION 3
CLOCK
CONSTRUCTION
1.
The clock source for IC614.(CPU : HD6413002)
is
X601
(10 MHz).
2.
The clock source for IC613 (Clock IC : NJU6355)
is
X603 (32.768 kHz).
3.
The clock sources for the digital audio system (AID, D/A, DPS, etc.) are
X301
(48.6 MHz) and
X901
(12.288 MHz).
[Regarding the clock
of
the digital audio system]
The condition
of
the digital audio system clock differs depending on whether the digital audio interface input
is
used (external) or not
(internal).
The difference between internal (System Setup Input = Analog) and external (System Setup Input = Digital or both, and input
is
made into
Digital IN)
is
the use of 12,288 MHz or the output
of
IC90l (Digital Audio Interface Receiver: pin
@)
MCK (256
fs)
of
CS8412. This
is
selected by the EXT/INT of pin @
of
IC906 (HC153). (When internal it
is
L.)
* Pin
@)
MCK
of
IC901 differs according
to
the sampling frequency of the signal that
is
input
to
the digital audio interface.
In
case
of
48
kHz it
is
12.288 MHz and
in
case
of
44.1 kHz it
is
11.2896 MHz.
* When the clock source
is
external, the oscillation
of
the internal crystal
X901
(12.288 MHz)
is
stopped in order
to
prevent interference
between the clocks.
IC305 (Digital
Filter:
CXD8482), which
is
based on this master clock, outputs LRCK (=lfs), which
is
the sampling frequency for the
whole system, from pin
@ or 64
fs
BCK from pin ® .
IC304 (AID converter: CXD8493) receives a clock
of
128
fs
from pin @
of
IC305 (Digital Filter: CXD8482) and operates.
The master clock (1024
fs)
of IC307 (D/A converter: CXD8505)
is
generated by the YCO block (Q904, Q905 and IC909, etc.).
It
uses
IC910
(PLL : TC8051AP) from LRCK, which
is
created by IC305 (Digital Filter: CXD8482), to lock. The 1024
fs
clock that
is
oscillated
by
YCO becomes the 256
fs
output from pin @ (256 fso) of IC307 (D/A converter: CXD8505), and it
is
further divided
by
IC907 and
IC908
(Prescaler : HC163) to become lfs, after which it
is
fed back
to
IC910 (PLL : TC8051AP)
to
form a loop.
The master clock
of
IC602 and 604 (DSP : CXD2707)
is
fixed at
X301
(48.6 MHz). The master clock of DSP
is
asynchronous with the
sampling frequency, but the processing of the
DPS signal
is
carried out at a LRCK
(lfs)
cycle.
* At the time of digital input (clock source = external) the master clock that
is
input
to
IC305 (Digital Filter: CXD8482)
is
changed
to
256
fs
which
is
output from pin
@)
of IC901 (Digital Audio Interface Receiver: CS8412), but all sequences besides that are the same
as
for
the internal operation.
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