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IC602, 604 CDX2707Q (DSP)
Pin No. Pin name
1 EA9
2
ECO
3
VDD
4
Vss
5,6
ECl-
2
7-9
EA13 - 15
10 TST
11
TDR
12
BFOT
13
CLKO
14 CLKI
15
Vss
16
TSO
17 TS1
18
TSA
19
LRKO
20 LRK1
21
BCKO
22
BCK1
23
BCT
24 LCT
25 SIA
26 SIB
27 SIC
28
VDD
29
Vss
30 SOA
31
SOB
32
SOC
33 EClO
34
ECll
35
ECl2
36 ECJ3
37
REDY
38
TRDT
39
XLAT
40 Vss
41
SCK
42
RVDT
43
SCLO
44
SCL1
I/O
0
0
-
-
0
0
I
I
0
0
I
-
I
I
I
I
I
I
I
0
I/O
I
I
I
-
-
0
0
0
I/O
I/O
I/O
I/O
0
0
I
-
0
I
0
0
SECTION 4
EXPLANATION
OF IC
TERMINALS
Description
External install RAM address. Not used (OPEN)
External install RAM address. Not used (OPEN)
Power
supply. (+5V)
Power supply. (GND)
External install RAM address. Not used
(OPEN)
External install RAM address. Not used (OPEN)
Test data input.
"L":
Normal
Test data input.
"L":
Normal
Master cIock buffer output. Not used
(OPEN)
Master cIock output. Not used (OPEN)
Master cIock input.
Power supply. (GND)
Test data input.
"L":
Normal
Test data input.
"L":
Normal
Test data input.
"L":
Normal
LRCK input.
LRCK input.
BCK input.
BCK input.
Frequency divider BCK output.
Counter input/frequency divider LRCK output for
SYNC DET.
Serial data input.
Serial data input.
Serial data input.
Power supply. (+5V)
Power supply. (GND)
Serial data output.
Serial data output.
Serial data output.
Terminal input/test data output for conditional jump.
Terminal input/test data output for conditional jump.
Terminal input/test data output for conditional jump. Not used (GND connection)
Terminal input/test data output for conditional jump. Not used (GND connection)
HCIF Readay signal output.
(Open drain)
HCIF data output.
HCIF data
• mode identification signal input.
Power supply. (GND)
HCIF shift cIock output.
HCIF data input.
Test data output. Not used
(OPEN)
Test data output. Not used (OPEN)
-
20-