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Post-Processing and Analysis Tool Sets
Data Communications
Theory of Operation
Use a logic analyzer to probe the
system’s parallel data buses (e.g.,
UTOPIA).
The analyzer needs access to:
• Data signals
• Qualifying signals
• Start of cell or packet bit
• Synchronous clock for the bus
The synchronous bus clock samples
data into the logic analyzer.
Qualifiers such as "Data Valid" allow
the logic analyzer to sample only on
events of interest instead of all
cycles.
With access to the "Start of Cell" or
"Start of Packet" bit on the data bus,
the analyzer starts looking at the
beginning of a cell or packet. With the
protocol definition set up by the user,
the logic analyzer can sequence down
into the cell or packet to find the
desired protocol field to trigger on.
UTOPIA Level 2
CPU
Custom/UTOPIA
PHY
PHY
PHY
PHY
PHY
PHY
PHY
ATM
Layer
ATM
Layer
ATM
Layer
ATM
Layer
Switch
Fabric
UTOPIA Level 1
Figure 5.5. Typical ATM Switch Design.