10 Chapter 1
Introduction
Utilities board
The environmental error interrupt and the 1.2 second delay provide the
system adequate time to read CSRs to determine the cause of the error,
log the condition in NVRAM, and display the condition on the attention
lightbar.
After the system is powered down, the Utilities board is still powered up,
but all outputs are disconnected from the system.
Environmental control
The Utilities board performs the following functions to control the node
environment.
Power-on
When the power switch is turned on, the outputs of the 48-Volt power
supplies become active. Several hundred milliseconds after the Utilities
board 5-Volt supply reaches its nominal level, the power-on circuit starts
powering up the other DC-to-DC converters of the node in succession.
The power-on circuit does not power up the node if an ASIC is installed
incorrectly (see “ASIC installation error” on page 18) or if an FPGA is not
configured (see “FPGA configuration and status” on page 19). It keeps
the system powered up unless an environmental condition occurs that
warrants a power-down.
Voltage margining
Voltage margin is divided into four groups called quadrants. The user
can margin quadrants separately. When setting the upper margin, for
example, all boards in that quadrant are margined for upper.
Clock margining
Parallel ports on the core logic microprocessor select the nominal, upper,
or external clock that drives the node.
JTAG interface
The JTAG interface supports a teststation and a mechanism to fanout
JTAG to all the boards in a node. It is used only for testing.
JTAG functions are described in the following sections.
