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LPDDR SDRAM MT46H64M16LFCK-5
Signal Name FPGA IO Comment
MCB1_DQ12 T17
MCB1_DQ13 T18
MCB1_DQ14 U17
MCB1_DQ15 U18
MCB1_UDQS N15 Data strobe for Upper Byte Data bus: Output with read data, input
with write data. DQS is edge-aligned with read data, center-aligned in
write data. It is used to capture data.
* As the memory device interface of Spartan-6 supports only one device, CS# signal is not
supported by Spartan-6 MCB. CS# is pulled LOW via an external 0 Ohm resistor.
! It is strongly recommended to check XILINX
TM
user guide UG388 about Spartan-6
TM
FPGA Memory Controller on XILINX
TM
website.
! It is strongly recommended to check XILINX
TM
user guide UG416 about Spartan-6
TM
FPGA Memory Interface Solutions on XILINX
TM
website.
User specific data can be stored in up to 128Mb of non-volatile Flash-memory. The
SPI- compliant interface guarantees ease of use and when speed matters
Macronix MX25L12845EMI-10G supports Q- SPI with data-rates up to 50 MByte/s in fast
read double transfer rate mode. Some examples on how to implement a SPI- compliant
interface with Spartan-6
TM
are available in chapter C.
Q- SPI Flash MX25L12845EMI-10G
Signal Name FPGA IO Comment
MX_CS_n T6 Active- low Chip Select.
MX_SCLK V4 Clock Input.
MX_SIO0 V6 Serial Data Input (SPI) / Serial Data IO (Dual- or Q- SPI).
MX_SIO1 T4 Serial Data Input (SPI) / Serial Data IO (Dual- or Q- SPI).
MX_SIO2 U7 Active- low Write Protect (SPI) / Serial Data IO (Dual- or Q-SPI).
MX_SIO3 V7 Not connect pin (SPI) / Serial Data IO (Dual- or Q-SPI).
Peripherals
USBS6 integrates several peripheral devices. Three system and five user- configurable
LEDs, one HEX rotary DIP switch and one USB to SERIAL UART are available. Power
supply status and FPGA configuration are observable through the system LEDs. The user-
USBS6 / C1030-5510 http://www.cesys.com/
User Doc V0.3 -11- preliminary