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projects can be created. Only one project can be active in one session.
Initializing sequence
The initializing sequence is a list of actions that must be executed in order to work with the
FPGA on the device. (The image shows an example initializing list of an EFM01, loading
our example design and let the LED blink for some seconds):
Figure 15: Initializing sequence
Sequence contents
UDKLab supports the following content for initialization:
• FPGA programming
• FPGA reset
• Register write
• Sleep
Without a design, an FPGA does nothing, so it must be loaded before usage. This can be
ensured in two ways:
USBS6 / C1030-5510 http://www.cesys.com/
User Doc V0.3 -55- preliminary