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HARDWARE-CIRCUITS OR ANY OTHER KIND OF ASIC OR PROGRAMMABLE LOGIC
DESIGN), EVEN IF THE COPYRIGHT HOLDER HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
Design “usbs6_soc”
An on-chip-bus system is implemented in this design. The VHDL source code shows you,
how to build a 32 Bit WISHBONE based shared bus architecture. All devices of the
WISHBONE system support only SINGLE READ / WRITE Cycles. Files and modules
having something to do with the WISHBONE system are labeled with the prefix “wb_”. The
WISHBONE master is labeled with the additional prefix “ma_” and the slaves are labeled
with “sl_”. There is a package for each module with the additional postfix “_pkg”. It contains
the appropriate VHDL component declaration / interface description as well as public
constants like register address offsets.
Files and modules
src/wishbone_pkg.vhd:
A package containing datatypes, constants, and components needed for the WISHBONE
system. There are VHDL subroutines for a WISHBONE master bus functional model
USBS6 / C1030-5510 http://www.cesys.com/
User Doc V0.3 -21- preliminary
Figure 8: WISHBONE system overview
FX2
FX2
MCB
MCB
BRAM
BRAM
INTERCONNECTION
INTERCONNECTION
32-Bit SoC
S S
S
Universal Data
Source/Sink
Ext.-Mem.
Access
LPDDR
Slave-FIFO
SPI Multi-I/O
M
S
On-Chip-Bus
Protocol
Engine
UART
UART
Xilinx ®
SIO
Macros
S
GPIO
GPIO
Connectors
LEDs
Hex-Enc.
FLASH
FLASH
Configuration
&
User Flash
Access
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