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The upper waveform demonstrates the behavior of app_fifo_wr_full_o and
app_fifo_wr_count_o when there is no transaction on the slave FIFO controller side of
the FIFO. During simultaneous FIFO-read- and FIFO-write-transactions, the signals do not
change. The signal app_fifo_wr_full_o will be cleared and app_fifo_wr_count_o
will decrease, if there are read-transactions at the slave FIFO controller side, but no write-
transactions at the application side.
The lower waveform demonstrates the behavior of app_fifo_rd_empty_o and
app_fifo_rd_count_o when there is no transaction at the slave FIFO controller side of
the FIFO. During simultaneous FIFO-read- and FIFO-write-transactions, the signals do not
change. The signal app_fifo_rd_empty_o will be cleared and
app_fifo_rd_count_o will increase, if there are write-transactions on the slave FIFO
controller side, but no read-transactions at the application side. Please note the one clock-
cycle delay between app_fifo_rd_i and app_fifo_rd_data_o!
The signals app_usb_h2p_pktcount_o[7:0] and app_usb_p2h_pktcount_o[7:0]
(not shown in figure 9) are useful to fit the 512 byte USB bulk packet alignment. They
are automatically incremented, if the appropriate read- (app_fifo_rd_i) or write-
strobe (app_fifo_wr_i) is asserted. These signals count 16 bit data words, not data
bytes! 512 byte alignment is turned into a 256 16 bit word alignment at this interface.
Please note, that using raw USB bulk transfers and slave FIFO transactions directly is not
recommended! It is just for background information. Use protocol based WISHBONE
interface instead!
USBS6 / C1030-5510 http://www.cesys.com/
User Doc V0.3 -24- preliminary
Figure 9: FIFO transactions of fx2_slfifo_ctrl at user logic side
app_fifo_wr_count_o
app_fifo_rd_count_o
app_fifo_wr_i
app_fifo_rd_i
app_fifo_wr_full_o
app_fifo_rd_empty_o
app_fifo_rd_data_o
app_fifo_wr_data_i
ifclk
D0 D1 D2 D3 D4
126
125124123122
127
ifclk
D0D1
D2
D3
D4
1
2345
0
FX-2 => FPGA FPGA => FX-2