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UDKLab
Introduction
UDKLab is a replacement of the former cesys-Monitor, as well as cesys-Lab and fpgaconv.
It is primary targeted to support FPGA designers by offering the possibility to read and write
values from and to an active design. It can further be used to write designs onto the
device's flash, so FPGA designs can load without host intervention. Additionally, designs
can be converted to C/C++ and C# arrays, which allows design embedding into an
application.
USBS6 / C1030-5510 http://www.cesys.com/
User Doc V0.3 -50- preliminary