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! It is strongly recommended to check XILINX
TM
UG381 about Spartan-6 FPGA SelectIO
Signal Standards on XILINX
TM
website.
Configuration
Configuration of USBS6 can be accomplished in several ways: JTAG, SPI-Flash or USB.
The default configuration mode is booting from SPI-Flash. After powering on the FPGA,
USBS6 always tries to configure itself from the attached Flash using SPI Master mode. If
no valid design is stored in the SPI-Flash the FPGA has to be configured via JTAG or USB.
JTAG configuration is supported at any time after the FPGA is properly powered on. For
downloading designs via JTAG ISE WebPACK from XILINX
TM
is recommended. The tool
can be downloaded from XILINX web page free of charge. As JTAG connector USBS6
implements a standard 2x7-Pin header with 2mm pitch which is compatible to recent
XILINX
TM
platform cables.
J2 JTAG connector
PIN Signal
Name
FPGA
IO
Comment PIN Signal
Name
FPGA
IO
Comment
1 GND -- Ground signal 2 VCCAUX -- 3.3V auxiliary supply.
3 GND -- Ground signal 4 TMS B18 Test Mode Select.
5 GND -- Ground signal 6 TCK A17 Test Clock.
7 GND -- Ground signal 8 TDO D16 Test Data Out.
9 GND -- Ground signal 10 TDI D15 Test Data In.
11 GND -- Ground signal 12 -- -- No connection.
13 GND -- Ground signal 14 -- -- No connection.
For further information on the different configuration solutions for XILINX
TM
SPARTAN-6
TM
USBS6 / C1030-5510 http://www.cesys.com/
User Doc V0.3 -7- preliminary
Figure 3: JTAG connector J2