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FPGA the reader is encouraged to take a look at the user guide UG380 on XILINX
TM
web
page.
USB2.0 controller
CYPRESS
TM
FX2LP
TM
is a highly integrated, low power USB2.0 microcontroller, that
integrates USB2.0 transceiver, serial interface engine (SIE), enhanced 8051 micro-
controller and a programmable peripheral interface. More information on usage of FX2LP
TM
in conjunction with Spartan-6 can be found in chapter C.
USB2.0 FX2LP
TM
Microcontroller CYPRESS
TM
CY7C68013A
Signal Name FPGA IO Comment
FX2_IFCLK V9 Clock input for both, FX2 and FPGA. 48MHz clock is provided by an
external oscillator.
FX2_SLWR U8 FX2 input, FIFO write-strobe.
FX2_SLRD T7 FX2 input, FIFO read-strobe.
FX2_SLOE V11 FX2 input, output-enable, activates FX2 data bus.
FX2_PKTEND V8 FX2 input, packet end control signal, causes FX2 to send data to host
at once, ignoring 512 byte alignment (so called “short packet”).
! Short packets sometimes lead to unpredictable behavior at host
side, wherefore short packets are not support!
FX2_FIFOADR0 R10
FX2 input, endpoint buffer addresses, only two endpoints are used:
EP2 (OUT, ADR[1:0] = b”00”) and EP6 (IN, ADR[1:0] = b”10”).
FX2_FIFOADR1 U3
FX2_FLAGA V16 FX2 output, EP2 “empty” flag.
FX2_FLAGB U16 FX2 output, EP2 “almost empty” flag.
FX2_FLAGC U11 FX2 output, EP6 “almost full” flag.
FX2_FD0 R11 16-Bit bidirectional FIFO data bus.
FX2_FD1 T14
FX2_FD2 V14
FX2_FD3 U5
FX2_FD4 V5
FX2_FD5 R3
FX2_FD6 T3
FX2_FD7 R5
FX2_FD8 N5
FX2_FD9 P6
FX2_FD10 P12
USBS6 / C1030-5510 http://www.cesys.com/
User Doc V0.3 -8- preliminary