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The WISHBONE signals in these illustrations and explanations are shown as simple bit
types or bit vector types, but in the VHDL code these signals could be encapsulated in
extended data types like arrays or records.
Example:
...
port map
(
...
ACK_I => intercon.masters.slave(2).ack,
...
Port ACK_I is connected to signal ack of element 2 of array slave, of record masters, of
record intercon.
Design “usbs6_bram”
This design is intended to demonstrate behavior of UDK software API resulting in
USBS6 / C1030-5510 http://www.cesys.com/
User Doc V0.3 -27- preliminary
Figure 10: WISHBONE transactions with WriteRegister() WriteBlock()
ReadRegister() ReadBlock()
Basic WISHBONE cycle
Master
Slave
CLK
STB
WE
ADR
32
DAT
32
M
ACK
DAT
32
S