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AD9912
Rev. D | Page 12 of 40
06763-015
100 1k 10k 100k 1M 10M 100M
FREQUENCY OFFSET (Hz)
–100
–110
–120
–130
–140
–150
PHASE NOISE (dBc/Hz)
800MHz
600MHz
RMS JITTER (100Hz TO 100MHz):
600MHz:
800MHz:
585fs
406fs
Figure 15. Absolute Phase Noise Using HSTL Driver,
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed),
HSTL Output Doubler Enabled
06763-016
100 1k 10k 100k 1M 10M 100M
FREQUENCY OFFSET (Hz)
–110
–120
–130
–140
–150
–160
PHASE NOISE (dBc/Hz)
150MHz
50MHz
10MHz
RMS JITTER (100Hz TO 20MHz):
150MHz:
50MHz:
308fs
737fs
Figure 16. Absolute Phase Noise Using CMOS Driver at 3.3 V,
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)
DDS Run at 200 MSPS for 10 MHz Plot
06763-017
100 1k 10k 100k 1M 10M 100M
FREQUENCY OFFSET (Hz)
–110
–120
–130
–140
–150
–160
PHASE NOISE (dBc/Hz)
50MHz
10MHz
RMS JITTER (100Hz TO 20MHz):
50MHz: 790fs
Figure 17. Absolute Phase Noise Using CMOS Driver at 1.8 V,
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)
06763-018
250 375 500 625 750 875 1000
SYSTEM CLOCK FREQUENCY (MHz)
800
700
600
500
400
300
200
100
0
POWER DISSIPATION (mW)
TOTAL
3.3V
1.8V
Figure 18. Power Dissipation vs. System Clock Frequency
(SYSCLK PLL Bypassed), f
OUT
= f
SYSCLK
/5, HSTL Driver On, CMOS Driver On,
SpurKiller Off
06763-019
0 100 200 300 400
OUTPUT FREQUENCY (MHz)
800
700
600
500
400
300
200
100
0
POWER DISSIPATION (mW)
TOTAL
3.3V
1.8V
Figure 19. Power Dissipation vs. Output Frequency
SYSCLK = 1 GHz (SYSCLK PLL Bypassed), HSTL Driver On,
CMOS Driver On, SpurKiller Off
06763-020
0 100 200 300 400 500
FREQUENCY (MHz)
–20
–30
–40
10
0
–10
–50
–60
–70
–80
–90
–100
SIGNAL POWER (dBm)
CARRIER:
SFDR W/O SPURKILLER:
SFDR WITH SPURKILLER:
FREQUENCY SPAN:
RESOLUTION BW:
VIDEO BW:
399MHz
–63.7dBc
–69.3dBc
500MHz
3kHz
30kHz
THESE TWO SPURS
ELIMINATED WITH
SPURKILLER
Figure 20. SFDR Comparison With and Without SpurKiller,
SYSCLK = 1 GHz, f
OUT
= 400 MHz