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AD9912
Rev. D | Page 37 of 40
Register 0x0503—Spur A (Continued)
Table 38.
Bits Bit Name Description
[7:0] Spur A phase Linear offset for Spur B phase.
Register 0x0504—Spur A (Continued)
Table 39.
Bits Bit Name Description
[8] Spur A phase Linear offset for Spur A phase.
Register 0x0505—Spur B
Table 40.
Bits Bit Name Description
7 HSR-B enable Harmonic Spur Reduction B enable.
6 Amplitude gain × 2 Setting this bit doubles the gain of the cancelling circuit and also doubles the minimum step size.
[5:4] Reserved Reserved.
[3:0] Spur B harmonic Spur B Harmonic 1 to Spur B Harmonic 15. Allows user to choose which harmonic to eliminate.
Register 0x0506—Spur B (Continued)
Table 41.
Bits Bit Name Description
[7:0] Spur B magnitude Linear multiplier for Spur B magnitude.
Register 0x0508—Spur B (Continued)
Table 42.
Bits Bit Name Description
[7:0] Spur B phase Linear offset for Spur B phase.
Register 0x0509—Spur B (Continued)
Table 43.
Bits Bit Name Description
8 Spur B phase Linear offset for Spur B phase.