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MPCMM0002 CMM—Module Components
Intel NetStructure
®
MPCMM0002 Chassis Management Module
Hardware TPS July 2007
18 Order Number: 309247-004US
PCI Bus Interface
PCI Local Bus Specification, Rev. 2.2 compliant
PCI-X Addendum to the PCI Local Bus Specification, Rev. 1.0a
64-bit/66 MHz Operation in PCI Mode
64-bit/133 MHz Operation in PCI-X Mode
Support 32-bit PCI Initiators and Targets
Four Split Read Requests as Initiator
Eight Split Read Requests as Target
64-bit Addressing Support
Memory Controller
PC200 Double Data Rate (DDR) SDRAM
Up to 1 GByte of 64-bit DDR SDRAM (128 MBytes on MPCMM0002)
Up to 512 MBytes of 32-bit DDR SDRAM
Single-bit Error Correction, Multi-bit Support (ECC)
1024 Byte Posted Memory Write Queue
40- and 72-bit wide Memory Interface
Address Translation Unit
2 KByte or 4 KByte Outbound Read Queue
4 KByte Outbound Write Queue
4 KByte Inbound Read and Write Queue
Connects Internal Bus to PCI/PCI-X Bus
DMA Controller
Two Independent Channels Connected to Internal Bus
Up to 1064 MByte/s Burst Support in PCI-X Mode
Up to 1600 MByte/s Burst Support for Internal Bus
Two 1 KB Queues in Ch-0 and Ch-1
232 Addressing Range on Internal Bus Interface
264 Addressing Range on PCI Interface
Application Accelerator Unit
Performs XOR on Read Data
Compute Parity Across Local Memory Blocks
1 KByte/512 Byte Store Queue
I
2
C Bus Interface Units
Two Separate I
2
C Units (one used on MPCMM0002)
Serial Bus
Master/Slave Capabilities
System Management Functions
SSP Serial Port
Full-duplex Synchronous Serial Interface
Supports 7.2 KHz to 1.84 MHz Bit Rates
Peripheral Performance
Monitoring Unit
One Dedicated Global Time Stamp Counter
Fourteen Programmable Event Counters
Three Control/Status Registers
Timers
Two Dual-programmable 32-bit Timers
Watchdog Timer
544-Ball, Plastic Ball Grid Array
(PBGA)
Eight General Purpose I/O Pins
Table 2. Processor Features (Sheet 2 of 2)