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MPCMM0002 CMM—Rear Connections
Intel NetStructure
®
MPCMM0002 Chassis Management Module
Hardware TPS July 2007
42 Order Number: 309247-004US
• BD_SEL# bit is set low indicating the CMM is properly inserted.
• OSL bit is set high indicating the OS is loading.
If one CMM detects an internal failure that cannot be corrected through software, it will
deassert its HLY# signal. If the faulty CMM is the active CMM, the standby CMM
becomes the active CMM as soon as it sees the HLYI# signal rise. HLY# de-asserts for
the following reasons: board removal, power goes unstable, watchdog timer fires,
board reset, OSL bit is de-asserted by firmware, or software sets fail bit.
Similarly, if one CMM is removed, its PRES# signal on the backplane will no longer be
held low and the other CMM will see a high PRESI# signal. Hardware on that CMM
quickly negotiates for it to become the active CMM.
In an active-standby mode, a communications path between the two CMMs over both
IPMB and Ethernet is needed for full synchronization.