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Altera Corporation 91
3232323232-Bit Instruction Set
2
32-Bit Instruction
Set
ST16d
Store 16-Bit Data To Memory (Computed Half-Word Pointer Address)
Operation: Not preceded by PFX :
hn
Mem32[align32(RA)] ←
hn
R0 where n = RA[1]
Preceded by PFX:
hn
Mem32[align32(RA + (σ(K) × 4))] ←
hn
R0 where n = RA[1]
Assembler Syntax: ST16d [%rA],%r0
Example: Not preceded by PFX:
FILL16 %r0,%g7 ; duplicate short of %g7 across %r0
ST16d [%o3],%r0 ; store %o3[1]th short int from
; %r0 to [%o3]
; second operand can only be %r0
Preceded by PFX:
FILL16 %r0,%g3
PFX 5
ST16d [%o3],%r0 ; same as above, offset
; 20 bytes in memory
Description: Not preceded by PFX:
Stores one of the two half-words of %r0 to memory at the half-word-aligned
address given by RA. The bits RA[1] selects which half-word in %r0 get stored
(half-word 1 is the most-significant). RA[0] is ignored.
ST16d may be used in combination with FILL16 to implement a two-instruction
half-word-store operation. Given a half-word held in bits 15..0 of any register %rX,
the following sequence writes this half-word to memory at the half-word-aligned
address given by RA:
FILL16 %r0,%rX
ST16d [%rA],%r0
Preceded by PFX:
The value in K is sign-extended and used as a word-scaled, signed offset. This
offset is added to the base-address RA and data is written to the resulting byte-
address.
Condition Codes: Flags: Unaffected
Instruction Format: Rw
Instruction Fields: A = Register index of operand RA
1514131211109876543210
0111111 0001 A
NVZC
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