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01111101111
01111110000 ST8d Rw
bn
Mem32 [align32(RA +(σ(K) × 4))] ←
bn
%r0
where n = RA[1..0]
01111110001 ST16d Rw
hn
Mem32 [align32(RA + (σ(K) × 4))] ←
hn
%r0
where n = RA[1]
01111110010 FILL8 Rw %r0 ← (
b0
RA :
b0
RA :
b0
RA : b
0
RA)
01111110011 FILL16 Rw %r0 ← (
h0
RA :
h0
RA)
01111110100 MSTEP Rw if (%r0[31] == 1) then %r0 ← (%r0 << 1) + RA else %r0
← (%r0 << 1)
01111110101 MUL Rw %r0 ← (%r0 & 0x0000.ffff) × (RA & 0x0000.ffff)
01111110110 SKPRz Rw Skip next instruction if:(RA ==0)
01111110111 SKPS i4w Skip next instruction if condition encoded by IMM4w is true
01111111000 WRCTL Rw CTLk ← RA
01111111001 RDCTL Rw RA ← CTLk
01111111010 SKPRnz Rw Skip next instruction if: (RA ! = 0)
01111111011
01111111100
01111111101
01111111110 JMP Rw PC ← (RA × 2)
01111111111 CALL Rw R15 ←((PC + 4) >> 1); PC ← (RA × 2)
100000 BR i11 PC ← PC + ((σ(IMM11) + 1) × 2)
100001
100010 BSR i11 PC ← PC + ((σ(IMM11) + 1) × 2);
%r15 ← ((PC + 4) >> 1)
10011 PFX i11 K ← IMM11 (K set to zero after next instruction)
1010 STP RPi5 Mem32[align32(RP + (σ(K : IMM5) × 4))] ← RA
1011 LDP RPi5 RA ← Mem32 [align32(RP + (σ(K : IMM5) × 4))]
110 STS Ri8 Mem32[align32(%sp + (IMM8 × 4) )] ← RA
111 LDS Ri8 RA ← Mem32 [align32(%sp + (IMM8 × 4))]
Table 17. 32-bit Major Opcode Table (Sheet 3 of 3)
Opcode Mnemonic Format Summary