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Altera Corporation 35
3232323232-Bit Instruction Set
2
32-Bit Instruction
Set
ADD
Add Without Carry
Operation: RA ← RA + RB
Assembler Syntax: ADD %rA,%rB
Example: ADD %L3,%g0 ; ADD %g0 to %L3
Description: Adds the contents of register A to register B and stores the result in register A.
Condition Codes: Flags:
N: Result bit 31
V: Signed-arithmetic overflow
Z: Set if result is zero; cleared otherwise
C: Carry-out of addition
Instruction Format: RR
Instruction Fields: A = Register index of RA operand
B = Register index of RB operand
1514131211109876543210
000000 B A
NVZC
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