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38 Altera Corporation
32-Bit Instruction Set
ANDN
Bitwise Logical AND NOT
Operation: Not preceded by PFX:
RA ← RA & ~RB
Preceded by PFX:
RA
← RA &~(0x00.00 : K: IMM5)
Assembler Syntax: Not preceded by PFX:
ANDN %rA,%rB
Preceded by PFX:
PFX %hi(const)
ANDN %rA,%lo(const)
Example: Not preceded by PFX:
ANDN %g0,%g1 ; %g0 gets %g0 & ~%g1
Preceded by PFX:
PFX %hi(16384)
ANDN %g0,%lo(16384) ; clear bit 14 of %g0
Description: Not preceded by PFX:
Logically-AND the individual bits in RA with the corresponding bits in the one’s-
complement of RB; store the result in RA.
Preceded by PFX:
When prefixed, the RB operand is replaced by an immediate constant formed by
concatenating the contents of the K-register (11 bits) with IMM5 (5 bits). This
16-bit value is zero-extended to 32 bits, then bitwise-inverted and bitwise-ANDed
with RA. The result is written back into RA.
Condition Codes: Flags:
N: Result bit 31
Z: Set if result is zero, cleared otherwise
Instruction Format: RR, Ri5
Instruction Fields: A = Register index of operand RA
B = Register index of operand RB
IMM5 = 5-bit immediate value
Not preceded by PFX (RR)
1514131211109876543210
001111 B A
Preceded by PFX (Ri5)
1514131211109876543210
001111 IMM5 A
NVZC
∆ – ∆ –