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Table 17. 32-bit Major Opcode Table (Sheet 1 of 3)
Opcode Mnemonic Format Summary
000000 ADD RR RA ← RA + RB
Flags affected: N, V, C, Z
000001 ADDI Ri5 RA ← RA + (0×00.00 : K : IMM5)
Flags affected: N, V, C, Z
000010 SUB RR RA ← RA – RB
Flags affected: N, V, C, Z
000011 SUBI Ri5 RA ← RA – (0×00.00 : K : IMM5)
Flags affected: N, V, C, Z
000100 CMP RR ∅ ← RA – RB
Flags affected: N, V, C, Z
000101 CMPI Ri5 ∅ ← RA – (0×00.00 : K : IMM5)
Flags affected: N, V, C, Z
000110 LSL RR RA ← (RA << RB [4..0]),
Zero-fill from right
000111 LSLI Ri5 RA ← (RA << IMM5),
Zero-fill from right
001000 LSR RR RA ← (RA >> RB [4..0]),
Zero-fill from left
001001 LSRI Ri5 RA ← (R >> IMM5),
Zero-fill form left
001010 ASR RR RA ← (RA >> RB [4..0]),
Fill from left with RA[31]
001011 ASRI Ri5 RA ← (RA >> IMM5),
Fill from left with RA[31]
001100 MOV RR RA ← RB
001101 MOVI Ri5 RA ← (0×00.00 : K : IMM5)
001110 AND RR
Ri5
RA ← RA & {RB, (0×00.00 : K : IMM5)}
Flags affected: N, Z
001111 ANDN RR,
Ri5
RA ← RA & ~({RB, (0×00.00 : K : IMM5)})
Flags affected: N, Z
010000 OR RR,
Ri5
RA ← RA | {RB, (0×00.00 : K : IMM5)}
Flags affected: N, Z
010001 XOR RR,
Ri5
RA ← RA ⊕ {RB, (0×00.00 : K : IMM5)}
Flags affected: N, Z
010010 BGEN Ri5 RA ← 2
IMM5
010011 EXT8d RR RA ← (0×00.00.00 :
bn
RA) where n = RB[1..0]
010100 SKP0 Ri5 Skip next instruction if: (RA [IMM5] == 0)
010101 SKP1 Ri5 Skip next instruction if: (RA [IMM5] == 1)
010110 LD RR RA ← Mem32 [align32( RB + (σ(K) × 4))]