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Altera Corporation 99
3232323232-Bit Instruction Set
2
32-Bit Instruction
Set
SUB
Subtract
Operation:
RA ← RA − RB
Assembler Syntax: SUB %rA,%rB
Example: SUB %i3,%g0 ; SUB %g0 from %i3
Description: Subtracts the contents of RB from RA, stores result in RA.
Condition Codes: Flags:
N: Result bit 31
V: Signed-arithmetic overflow
Z: Set if result is zero; cleared otherwise
C: Set if there was a borrow from the subtraction; cleared otherwise
Instruction Format: RR
Instruction Fields: A = Register index of RA operand
B = Register index of RB operand
1514131211109876543210
000010 B A
NVZC
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