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Altera Corporation 97
3232323232-Bit Instruction Set
2
32-Bit Instruction
Set
STS16s
Store 16-bit Data To Memory (Stack-Addressing Mode)
Operation:
hn
Mem32[align32(%sp + IMM9 × 2)] ←
hn
R0 where n = IMM9[0]
Assembler Syntax: STS16s [%sp,IMM9],%r0
Example: STS16s [%sp,7],%r0 ; can only be %sp and %r0
Description: Stores one of the two half-words of %r0 to memory at the half-word-aligned
address given by (%sp plus IMM9 × 2). The least-significant bit of IMM9 selects
which half-word of %r0 is stored (half-word 1 is most significant).
STS16s may be used in combination with FILL16 to implement a 16-bit store
operation to a half-word offset from the stack-pointer in a 1Kbyte range. Given a
half-word held in bits 15..0 of any register %rX, the following sequence writes this
half-word to memory at the half-word-offset Y from %sp (%sp presumed to hold
a word-aligned address):
FILL16 %r0,%rX
STS16s [%sp,Y],%r0
Condition Codes: Flags: Unaffected
Instruction Format: i9
Instruction Fields: IMM9 = 9-bit immediate value
1514131211109876543210
011001 IMM9 0
NVZC
−−−−