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Altera Corporation 103
3232323232-Bit Instruction Set
2
32-Bit Instruction
Set
TRET
Trap Return
Operation: PC ← (RA << 1)
STATUS ← ISTATUS
Assembler Syntax: TRET %ra
Example: TRET %o7 ; return from TRAP
Description: Execution is transferred to the address given by (RA << 1). The value written in
%o7 by TRAP is suitable for use as a return-address without modification.
The value in ISTATUS is copied into the STATUS register (this restores the pre-
TRAP register window, because CWP is part of STATUS).
Condition Codes: Flags: Unaffected
Instruction Format: Rw
Instruction Fields: A = Register index of operand RA
1514131211109876543210
011111 01110 A
NVZC
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