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42 Altera Corporation
32-Bit Instruction Set
BR
Branch
Operation: PC ← PC + ((σ(IMM11) + 1) << 1)
Assembler Syntax: BR addr
Example: BR MainLoop
NOP ; (delay slot)
Description: The offset given by IMM11 is interpreted as a signed number of half-words
(instructions) relative to the instruction immediately following BR. Program control
is transferred to instruction at this offset.
Condition Codes: Flags: Unaffected
Delay Slot Behavior: The instruction immediately following BR (BR’s delay slot) is executed after BR,
but before the destination instruction. There are restrictions on which instructions
may be used as a delay slot. (Refer to “Branch Delay Slots” on page 23)
Instruction Format: i11
Instruction Fields: IMM11 = 11-bit immediate value
1514131211109876543210
10000 IMM11
NVZC
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