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44 Altera Corporation
32-Bit Instruction Set
CALL
Call Subroutine
Operation: %o7 ← ((PC + 4) >> 1)
PC ← (RA << 1)
Assembler Syntax: CALL %rA
Example: CALL %g0
NOP ; (delay slot)
Description: The value of RA is shifted left by one and transferred into PC. RA contains the
address of the called subroutine right-shifted by one bit. The return-address is the
address of the second subsequent instruction. Return-address is shifted right one
bit and stored in %o7. The right-shifted value stored in %o7 is a destination
suitable for direct use by JMP without modification.
Condition Codes: Flags: Unaffected
Delay Slot Behavior: The instruction immediately following CALL (CALL’s delay slot) is executed after
CALL, but before the destination instruction. There are restrictions on which
instructions may be used as a delay slot. (Refer to “Branch Delay Slots” on
page 23)
Instruction Format: Rw
Instruction Fields: A = Register index of operand RA
1514131211109876543210
011111 11111 A
NVZC
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