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GettingOverview
Overview
1
Pipeline Operation
The Nios CPU is pipelined RISC architecture. The pipeline
implementation is hidden from software except for branch delay slots and
when CWP is modified by a WRCTL direct write. The pipeline stages
include:
■ Instruction Fetch—the Nios CPU issues an address, and the memory
subsystem then returns the instruction stored at the issued address.
■ Instruction Decode / Operand Fetch—the fetched instruction is
decoded. If there are register operands, they are read from the
register file. A dedicated branch-target adder computes the
destination address for BR and BSR instructions.
■ Execute—the operands and control bits are presented to the ALU.
The ALU then computes a result.
■ Write-back—the ALU result is written back into the destination
register when applicable.
Branch Delay Slots
A branch delay slot is defined as the instruction immediately after a BR,
BSR, CALL, or JMP instruction. A branch delay slot is executed after the
branch instruction but before the branch-target instruction. Table 15
illustrates a branch delay-slot for a BR instruction.
Table 15. BR Branch Delay Slot Example
…
(a) ADD %g2, %g3
(b) BR Target
(c) ADD %g4, %g5
(d) ADD %g6, %g7
…
Target:
(e) ADD %g8, %g9
Branch Delay Slot