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16 Altera Corporation
Overview
Exceptions
The topics in this section include a description of the following:
■ Exception vector table
■ How external hardware interrupts, internal exceptions, register
window underflow, register window overflow and TRAP
instructions are handled
■ Direct software exceptions (TRAP) and exception processing
sequence
Exception Handling Overview
The Nios processor allows up to 64 vectored exceptions. Exceptions can be
enabled or disabled globally by the IE control-bit in the STATUS register,
or selectively enabled on a priority basis by the IPRI field in the STATUS
register. Exceptions can be generated from any of three sources: external
hardware interrupts, internal exceptions or explicit software TRAP
instructions.
The Nios exception-processing model allows precise handling of all
internally generated exceptions. That is, the exception-transfer
mechanism leaves the exception-handling subroutine with enough
information to restore the status of the interrupted program as if nothing
had happened. Internal exceptions are generated if a SAVE or RESTORE
instruction causes a register-window underflow or overflow,
respectively.
Exception-handling subroutines always execute in a newly opened
register window, allowing very low interrupt latency. The exception
handler does not need to manually preserve the interruptee’s register
contents.
Exception Vector Table
The exception vector table is a set of 64 exception-handler addresses. On a
32-bit Nios CPU each entry is 4 bytes and on a 16-bit Nios CPU each entry
is 2 bytes. The base-address of the exception vector table is configurable.
When the Nios CPU processes exception number n, it fetches the nth entry
from the exception vector table, doubles the fetched value and then loads
the results into the PC.
The exception vector table can physically reside in RAM or ROM,
depending on the hardware memory map of the target system. A ROM
exception vector table will not require run-time initialization.