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24 Altera Corporation
Overview
After branch instruction (b) is taken, instruction (c) is executed before
control is transferred to the branch target (e). The execution sequence of
the above code fragment would be (a), (b), (c), and (e). Instruction (c) is
instruction (b)’s branch delay slot. Instruction (d) is not executed. Most
instructions can be used as a branch delay slot except for those listed
below:
■ BR
■ BSR
■ CALL
■ IF1
■ IF0
■ IFRnz
■ IFRz
■ IFS
■ JMP
■ LRET
■ PFX
■ RET
■ SKP1
■ SKP0
■ SKPRnz
■ SKPRz
■ SKPS
■ TRET
■ TRAP
Direct CWP Manipulation
Every WRCTL instruction that modifies the STATUS register (%ctl0) must
be followed by a NOP instruction.