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Altera Corporation 39
3232323232-Bit Instruction Set
2
32-Bit Instruction
Set
ASR
Arithmetic Shift Right
Operation: RA ← (RA >> RB[4..0]), fill from left with RA[31]
Assembler Syntax: ASR %rA,%rB
Example: ASR %L3,%g0 ; shift %L3 right by %g0 bits
Description: Arithmetically shift right the value in RA by the value of RB; store the result in RA.
Bits 31..5 of RB are ignored. If the value in RB[4..0] is 31, RA will be zero or
negative one depending on the original sign of RA.
Condition Codes: Flags: Unaffected
Instruction Format: RR
Instruction Fields: A = Register index of RA operand
B = Register index of RB operand
1514131211109876543210
001010 B A
NVZC
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