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Altera Corporation 59
3232323232-Bit Instruction Set
2
32-Bit Instruction
Set
LD
Load 32-bit Data From Memory
Operation: Not preceded by PFX:
RA ← Mem32[align32(RB)]
Preceded by PFX:
RA ← Mem32[align32(RB +σ(K) × 4))]
Assembler Syntax: LD %rA,[%rB]
Example: Not preceded by PFX:
LD %g0,[%i3] ; load word at [%i3] into %g0
Preceded by PFX:
PFX 7 ; word offset
LD %g0,[%i3] ; load word at [%i3+28] into %g0
Description: Not preceded by PFX:
Loads a 32-bit data value from memory into RA. Data is always read from a word-
aligned address given by bits 31..2 of RB (the two LSBs of RB are ignored).
Preceded by PFX:
The value in K is sign-extended and used as a word-scaled, signed offset. This
offset is added to the base-address RB (bits 1..0 ignored), and data is read from
the resulting word-aligned address.
Condition Codes: Flags: Unaffected
Instruction Format: RR
Instruction Fields: A = Register index of operand RA
B = Register index of operand RB
1514131211109876543210
010110 B A
NVZC
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