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12 Altera Corporation
Overview
Full Width Register-Indirect
The LD and ST instructions can load and store, respectively, a full native-
word to or from a register using another register to specify the address.
The address is first aligned downward to a native-word aligned address,
as described in the “Memory Access Overview” section. The K register is
treated as a signed offset, in native words, from the native-word aligned
value of the address register.
Partial Width Register-Indirect
There are no instructions that read a partial word. To read a partial word,
you must combine a full width register-indirect read instruction with an
extraction instruction, EXT8d, EXT8s, EXT16d (32-bit Nios CPU only) or
EXT16s (32-bit Nios CPU only).
Several instructions can write a partial word. Each of these instructions
has a static and a dynamic variant. The position within both the source
register and the native-word of memory is determined by the low bits of
an addressing register. In the case of a static variant, the position within
both the source register and the native-word of memory is determined by
a 1- or 2-bit immediate operand to the instruction. As with full width
register-indirect addressing, the K register is treated as a signed offset in
native words from the native-word aligned value of the address register.
The partial width register-indirect instructions all use %r0 as the source of
data to write. These instructions are convenient to use in conjunction with
the FILL8 or FILL16 (32-bit Nios CPU only) instructions.
* 32-bit Nios CPU only
Table 11. Instructions Using Full Width Register-indirect Addressing
Instruction Address Register Data Register
LD Any Any
ST Any Any
Table 12. Instructions Using Partial Width Register-indirect Addressing
Instruction Address Register Data Register Byte/Half-word Selection
ST8s Any %r0 Immediate
ST16s* Any %r0 Immediate
ST8d Any %r0 Low bits of address register
ST16d* Any %r0 Low bits of address register