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108 Altera Corporation
F
FILL16 instruction 51
FILL8 instruction 52
Full Width Register-Indirect with Offset 13
G
General-Purpose Registers 2
GNU Compiler/Assembler
Pseudo-Instructions 31
H
Half-Word Extract (Dynamic) 47
Half-Word Extract (Static) 48
Half-Word Fill 51
I
IF0 instruction 53
IF1 instruction 54
IFRnz instruction 55
IFRz instruction 56
IFS instruction 57
Instruction Format 26
Instruction Set 2
Internal Exception Sources 17
Interrupt Enable (IE) 5
Interrupt Priority (IPRI) 5
ISTATUS (%ctl1) 6
J
JMP instruction 58
L
LD instruction 59
LDP instruction 60
LDS instruction 61
Load 32-bit Data From Memory 59
Load 32-bit Data From Memory
(Pointer Addressing Mode) 60
Load 32-bit Data From Memory
(Stack Addressing Mode) 61
Logical Not 74
Logical Shift Left 63
Logical Shift Left Immediate 64
Logical Shift Right 65
Logical Shift Right Immediate 66
LRET instruction 62
LSL instruction 63
LSLI instruction 64
LSR instruction 65
LSRI instruction 66
M
Memory Access Overview 7
MOV instruction 67, 73
Move Immediate 69
Move Immediate Into High Half-Word 68
MOVHI instruction 68
MOVI instruction 69
MSTEP instruction 70
MUL instruction 71
Multiply 71
Multiply-Step 70
N
NEG instruction 72
Nios CPU Block Diagram 22
Nios CPU Overview 1
NOP Instruction 73
NOT instruction 74
Notation Details 25
O
OR instruction 75
P
Partial Width Register-Indirect 12
Partial Width Register-Indirect with Offset 13
PFX instruction 76
Pipeline Implementation 22
Pipeline Operation 23
Prefix 76
Program-Flow Control 14
Programmer’s Model 3
R
RDCTL instruction 77
Read Control Register 77
Reading from Memory (or Peripherals) 8
Register Groups 2
Register Overview 2
Register Window Overflow 18
Register Window Underflow 17
Register Window Usage 20
Register-to-Register Move 67
Relative-Branch Instructions 14
Restore Caller’s Register Window 78
RESTORE instruction 78
RET instruction 79
Return-Address 21
RLC instruction 80
Rotate Left Through Carry 80