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94 Altera Corporation
32-Bit Instruction Set
ST8s
Store 8-bit Data To Memory (Static Byte-Offset Address)
Operation: Not preceded by PFX:
bn
Mem32[align32(RA)] ←
bn
R0 where n = IMM2
Preceded by PFX:
bn
Mem32[align32(RA + (σ(K) × 4))] ←
bn
R0 where n = IMM2
Assembler Syntax: ST8s [%rA],%r0,IMM2
Example: Not preceded by PFX:
MOVI %g4,12
ST8s [%g4],%r0,3 ; store high byte of %r0 to mem[15]
Preceded by PFX:
PFX 9
ST8s [%g4],%r0,2 ; store byte 2 of %r0 to
; mem[%g4 + 36 + 2]
Description: Not preceded by PFX:
Stores one of the four bytes of %r0 to memory at the byte-address given by
(RA[31..2] plus IMM2). The two bits RA[1..0] are ignored. IMM2 selects which
byte of %r0 is stored (byte 3 is most significant).
ST8s may be used in combination with FILL8 to implement a byte-store operation
to a byte-offset from a word-aligned base pointer. Given a byte held in bits 7..0 of
any register %rX, the following sequence writes this byte to memory at the byte-
address given by (RA + Y ) (RA presumed to hold a word-aligned pointer):
FILL8 %r0,%rX
PFX Y >> 2
ST8s [%rA],%r0,Y &3
Preceded by PFX:
A 13-bit signed, byte-scaled offset is formed by concatenating K with IMM2. This
offset (K : IMM2) is sign-extended to 32 bits and used as the byte-offset for the
ST-operation.
Condition Codes: Flags: Unaffected
Instruction Format: Ri2u
Instruction Fields: A = Register index of operand RA
IMM2 = 2-bit immediate value
1514131211109876543210
011101100 IMM2 A
NVZC
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