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Altera Corporation 79
3232323232-Bit Instruction Set
2
32-Bit Instruction
Set
RET
Equivalent to JMP %i7
Operation:
PC ← (%i7 << 1)
Assembler Syntax: RET
Example: RET ; return
RESTORE ; (restores caller’s register window)
Description: Jump to the target-address given by (%i7 << 1). Note that the target address will
always be half-word aligned for any value of %i7.
Condition Codes: Flags: Unaffected
Delay Slot Behavior: The instruction immediately following RET (RET’s delay slot) is executed after
RET, but before the destination instruction. There are restrictions on which
instructions may be used as a delay slot (Refer to “Branch Delay Slots” on
page 23).
Instruction Format: Rw
Instruction Fields: None (always uses %i7)
1514131211109876543210
0111111111011111
NVZC
−−−−