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Altera Corporation xi
List of Tables
Table 1. Revision History............................................................................................................................iii
Table 2. How to Contact Altera.................................................................................................................. iv
Table 3. Conventions .....................................................................................................................................v
Table 4. Nios CPU Architecture...................................................................................................................1
Table 5. Register Groups...............................................................................................................................2
Table 6. Programmer’s Model......................................................................................................................3
Table 7. Condition Code Flags.....................................................................................................................6
Table 8. Typical 32-bit Nios CPU Program/Data Memory at Address 0x0100...................................7
Table 9. N-bit-wide Peripheral at Address 0x0100 (32-bit Nios CPU)...................................................7
Table 10. Instructions Using 5/16-bit Immediate Values ........................................................................11
Table 11. Instructions Using Full Width Register-indirect Addressing.................................................12
Table 12. Instructions Using Partial Width Register-indirect Addressing............................................12
Table 13. Instructions Using Full Width Register-indirect with Offset Addressing............................13
Table 14. Instructions Using Partial Width Register-indirect with Offset Addressing .......................14
Table 15. BR Branch Delay Slot Example....................................................................................................23
Table 16. Notation Details.............................................................................................................................25
Table 17. 32-bit Major Opcode Table...........................................................................................................28
Table 18. GNU Compiler/Assembler Pseudo-instructions.....................................................................31