Filter
Top Products
Altera Corporation 43
3232323232-Bit Instruction Set
2
32-Bit Instruction
Set
BSR
Branch To Subroutine
Operation: %o7 ← ((PC + 4) >> 1)
PC ← PC + ((σ(IMM11)+1)<<1)
Assembler Syntax: BSR addr
Example: BSR SendCharacter
NOP ; (delay slot)
Description: The offset given by IMM11 is interpreted as a signed number of half-words
(instructions) relative to the instruction immediately following BR. Program control
is transferred to instruction at this offset. The return-address is the address of the
BSR instruction plus four, which is the address of the second subsequent
instruction. The return-address is shifted right one bit and stored in %o7. The
right-shifted value stored in %o7 is a destination suitable for direct use by JMP
without modification.
Condition Codes: Flags: Unaffected
Delay Slot Behavior: The instruction immediately following BSR (BSR’s delay slot) is executed after
BSR, but before the destination instruction. There are restrictions on which
instructions may be used as a delay slot. (Refer to “Branch Delay Slots” on
page 23)
Instruction Format: i11
Instruction Fields: IMM11 = 11-bit immediate value
1514131211109876543210
10001 IMM11
NVZC
−−−−