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CONTROL REGISTERS S3C84E5/C84E9/P84E9
4-40
UARTPND — UART Pending and parity control F4H Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write – – R/W R/W – – R/W R/W
.7–.6 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0)
.5 UART Parity Enable/Disable (PEN)
0 Disable
1 Enable
.4 UART Receive Parity Error (RPE)
0 No error
1 Parity error
.3–.2 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0)
.1 UART Receive Interrupt Pending Flag
0 Not pending
0 Clear pending bit (when write)
1 Interrupt pending
.0 UART Transmit Interrupt Pending Flag
0 Not pending
0 Clear pending bit (when write)
1 Interrupt pending
NOTES:
1. In order to clear a data transmit or receive interrupt pending flag, you must write a "0" to the appropriate pending bit.
2. To avoid programming errors, we recommend using load instruction (except for LDB), when manipulating UARTPND
values.
3. Parity enable and parity error check can be available in 9-bit UART mode (Mode 2) only.
4. Parity error bit (RPE) will be refreshed whenever 8th receive data bit has been shifted.