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INSTRUCTION SET S3C84E5/C84E9/P84E9
6-46
IRET — Interrupt Return
IRET IRET (Normal) RET (Fast)
Operation: FLAGS ← @SP PC ↔ IP
SP ← SP + 1 FLAGS ← FLAGS'
PC ← @SP FIS ← 0
SP ← SP + 2
SYM(0) ← 1
This instruction is used at the end of an interrupt service routine. It restores the flag register and the
program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the fast
interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast interrupt
occurred, IRET clears the FIS bit that was set at the beginning of the service routine.
Flags: All flags are restored to their original settings (that is, the settings before the interrupt occurred).
Format:
IRET
(Normal)
Bytes Cycles Opcode
(Hex)
opc 1 12 BF
IRET
(Fast)
Bytes Cycles Opcode
(Hex)
opc 1 6 BF
Example: In the figure below, the instruction pointer is initially loaded with 100H in the main program before
interrupt are enabled. When an interrupt occurs, the program counter and the instruction pointer
are swapped. This causes the PC to jump to the address 100H and the IP to keep the return
address. The last instruction in the service routine is normally a jump to IRET at the address
FFH.
This loads the instruction pointer with 100H "again" and causes the program counter to jump
back to the main program. Now, the next interrupt can occur and the IP is still correct at 100H.
IRET
Interrupt
Service
Routine
JP to FFH
0H
FFH
100H
FFFFH
NOTE: In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay
attention to the order of the last tow instruction. The IRET cannot be immediately proceeded by an
instruction which clears the interrupt status (as with a reset of the IPR register).