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S3C84E5/C84E9/P84E9 INTERRUPT STRUCTURE
5-3
S3C84E5/C84E9/P84E9 INTERRUPT STRUCTURE
The S3C84E5/C84E9/P84E9 microcontroller supports twenty-one interrupt sources. All of the interrupt sources have
a corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device-specific
interrupt structure, as shown in Figure 5-2.
When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which contending
interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt with the lowest
vector address is usually processed first (The relative priorities of multiple interrupts within a single level are fixed in
hardware).
When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled and the
program counter value and status flags are pushed to stack. The starting address of the service routine is fetched
from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service
routine is executed.