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ELECTRICAL DATA S3C84E5/C84E9/P84E9
17-10
Table 17-10. UART Timing Characteristics in Mode 0 (10 MHz)
(T
A
= – 25 °C to + 85 °C, V
DD
= V
LVR
to 5.5 V, Load capacitance = 80 pF)
Parameter Symbol Min Typ. Max Unit
Serial port clock cycle time
t
SCK
500
t
CPU
× 6
700
Output data setup to clock rising edge
t
S1
300
t
CPU
× 5
–
Clock rising edge to input data valid
t
S2
– – 300
Output data hold after clock rising edge
t
H1
t
CPU
– 50 t
CPU
–
Input data hold after clock rising edge
t
H2
0 – –
Serial port clock High, Low level width
t
HIGH
, t
LOW
200
t
CPU
× 3
400
ns
NOTES:
1. All timings are in nanoseconds (ns) and assume a 10-MHz CPU clock frequency.
2. The unit t
CPU
means one CPU clock period.
0.2 V
DD
0.8 V
DD
t
HIGH
t
LOW
t
SCK
Figure 17-7. Waveform for UART Timing Characteristics